This invention relates generally to semiconductor electrically erasable programmable read only memories (EEprom), and specifically to semiconductor structures of such memories and processes of making them.
An electrically programmable read only memory (Eprom) utilizes a floating (unconnected) conductive gate, in a field effect transistor structure, positioned over but insulated from a channel region in a semiconductor substrate, between source and drain regions. A control gate is then provided over the floating gate, but also insulated therefrom. The threshold voltage characteristic of the transistor is controlled by the amount of charge that is retained on the floating gate. That is, the minimum amount of voltage (threshold) that must be applied to the control gate before the transistor is turned "on" to permit conduction between its source and drain regions is controlled by the level of charge on the floating gate. The transistor is programmed to one of two states by accelerating electrons from the substrate channel region, through a thin gate dielectric and onto the floating gate.
The memory cell transistor's state is read by placing an operating voltage across its source and drain and on its control gate, and then detecting the level of current flowing between the source and drain. The level of current tells whether the device is programmed to be "on" or "off" at the control gate voltage selected. A specific, single cell in a two-dimensional array of Eprom cells is addressed for reading by application of a source-drain voltage to source and drain lines in a column containing the cell being addressed, and application of a control gate voltage to the control gates in a row containing the cell being addressed.
Early Eprom devices were erasable by exposure to ultraviolet light. More recently, the transistor cells have been made to be electrically erasable, and thus termed an electrically erasable and programmable read only memory (EEprom). Early EEprom cells were electrically erased by transfer of charge from the floating gate to the transistor drain through a very thin tunnel dielectric. This is accomplished by application of appropriate voltages to the transistor's source, drain and control gate. More recently, EEprom memory cells are provided with a separate, third gate for accomplishing the erasing. An erase gate passes through each memory cell transistor closely adjacent to a surface of the floating gate but insulated therefrom by a thin tunnel dielectric. Charge is then removed from the floating gate of a cell to the erase gate, when appropriate voltages are applied to all the transistor elements. An array of such EEprom cells are generally referred to as a Flash EEprom array because an entire array of cells, or significant group of cells, is erased simultaneously (i.e., in a flash).
Copending patent application Ser. No. 204,175 of Dr. Eliyahou Harari, filed June 8, 1988, contains a detailed discussion, with citations to the literature, of the prior art development of Eprom and EEprom devices in a section entitled "Detailed Description of the Prior Art," with respect to its FIGS. 1-4.
It is a primary object of the present invention to provide EEprom cell and array structures and processes for making them that result in cells of reduced size so their density on a semiconductor chip can be increased.
It is also an object of the invention that the structures be highly manufacturable, reliable, scalable, repeatable and reproducible with a very high yield.
It is yet another object of the present invention to provide EEprom semiconductor chips that are useful as a solid state memory that can replace magnetic disk storage devices.
Another object of the present invention is to provide a process with an increased insensitivity to misalignment of masks used to manufacture the semiconductor devices.
Further, it is an object of the present invention to provide an EEprom structure capable of an increased number of program/read cycles that it can endure.
Additionally, it is an object of the present invention to provide an EEprom structure with a fast response to programming and/or erasing.
Another object of the invention is to provide improved semiconductor processing techniques and structures.